snippet spinal_Mux "Mux cond" 
${1:val} := Mux(${2:cond}, ${3:value1}, ${4:value2})
endsnippet

snippet spinal_reg "generate register"
val ${1:counter} = Reg(${2:UInt(8 bits)}) init(0)
endsnippet

snippet spinal_counter "start and end inclusive, up counter" b

endsnippet

snippet spinal_fsm_template "style B"
val fsm = new StateMachine{
  val IDLE = new State with EntryPoint
  val STATEA = new State
  val STATEB = new State

  IDLE 
    .onEntry()  
    .whenIsActive{

    }
    .whenIsNext{
    
    }
    .onExit()  
}
endsnippet

snippet spinal_sub_fsm "fsm state" b
  ${1:IDLE} 
    .onEntry()  
    .whenIsActive{

    }
    .whenIsNext{
    
    }
    .onExit()  
endsnippet

snippet spinal_generate_verilog "generate verilog file"
object ${1:test}RTL {
    def main(args: Array[String]) {
    SpinalConfig(
      defaultConfigForClockDomains = ClockDomainConfig(resetKind = BOOT),
      defaultClockDomainFrequency = FixedFrequency(12 MHz),
      genLineComments = false,
	  nameWhenByFile = false,
      headerWithRepoHash = false,
      targetDirectory = "rtl" )
      .generateVerilog( new $1 )
    }
}
endsnippet

snippet spinal_module_template "include design and simulation"
import spinal.lib._
import spinal.core._
import spinal.core.sim._

class ${1:name} extends Component {
  val io = new Bundle {
    val bit0 = in Bool()
    val bit1 = out Bool()
    val data = out UInt(8 bits)
  }
  noIoPrefix()

  // logic
}

object $1RTL {
  def main(args: Array[String]) {
    SpinalConfig( 
      defaultConfigForClockDomains = ClockDomainConfig(resetKind = BOOT),
      defaultClockDomainFrequency = FixedFrequency(10 MHz),
      genLineComments = false,
	  nameWhenByFile = false,
      headerWithRepoHash = false,
      targetDirectory = "rtl" )
      .generateVerilog( new $1 )
  }
}

object $1Sim extends App{
  val spinalConfig = SpinalConfig(
    defaultConfigForClockDomains = ClockDomainConfig(resetKind = BOOT),
    defaultClockDomainFrequency = FixedFrequency(10 MHz)
  )

  SimConfig.withConfig(spinalConfig)
    .withWave
    .workspacePath("./simWorkspace")
    .compile(new $1)
    .doSim{ dut =>
      dut.clockDomain.forkStimulus(10)   // unit: ps
      for(i <- 0 to 3) {
        dut.clockDomain.waitSampling()
      }
  }
}
endsnippet

snippet spinal_clock_domain "clock demain config"
val ${1:myClockDomain} = ClockDomain (
    clock  = io.clk,
    reset  = io.rstn,
	frequency = FixedFrequency(100 MHz),
    config = ClockDomainConfig(
	clockEdge           = RISING,
	resetKind           = ASYNC,
	resetActiveLevel    = LOW
    )
)
endsnippet


snippet io "declare port" b
val io = new Bundle {
  val enable = in Bool()
  val data = out UInt(8 bits)
}
endsnippet


snippet spinal_module_blackbox "blackbox"
class ${1:Blackbox} extends BlackBox {
    val io = new Bundle {
    val enable = in Bool()
    val data = out UInt(8 bits)
    }
    noIoPrefix()
}
endsnippet


snippet bool "val b1 = Bool() \ val b2 = False \ val b3 = Bool(5 > 12)" 

endsnippet

snippet spinal_bits "does not convey any arithmetic meaning"
val myBits  = Bits()     // the size is inferred
val myBits1 = Bits(32 bits)
val myBits2 = B(25, 8 bits)
val myBits3 = B"8'xFF"   
endsnippet


snippet spinal_usage_bool "how to use bool"
// Declaration
val myBool_1 = Bool()        // Create a Bool
myBool_1 := False            // := is the assignment operator
val myBool_2 = False         // Equivalent to the code above
val myBool_3 = Bool(5 > 12)  // Use a Scala Boolean to create a Bool

x.setWhen(cond)		// Set x when cond is True
x.clearWhen(cond)	// Clear x when cond is True
x.riseWhen(cond)	// Set x when x is False and cond is True
x.fallWhen(cond)	// Clear x when x is True and cond is True
endsnippet

snippet spinal_sim_demo "spinalHdl simulation template" b
import spinal.lib._
import spinal.core._
import spinal.core.sim._

object ${1:Identity}Sim extends App{
  val spinalConfig = SpinalConfig(
    defaultConfigForClockDomains = ClockDomainConfig(resetKind = BOOT),
    defaultClockDomainFrequency = FixedFrequency(10 MHz)
  )

  SimConfig
    .withConfig(spinalConfig)
    .withWave
    .workspacePath("./simWorkspace")
    .compile(new ${1:Identity}(3))
    .doSim{ dut =>
      dut.clockDomain.forkStimulus(10)   // unit: ps
      for(i <- 0 to 3) {
        dut.clockDomain.waitSampling()
      }
  }
}
endsnippet
